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Simulation Advice II

Here is some more general advice for simulation of HDL code. No respect is paid to verification methodologies like UVM or OSVVM. Most of it is obvious, but it helps my memory when I write these things down.

  • Use one big record type to define what is part of a test case.
    Then define multiple constants of the test case record type, one for each test case.
    Scheduling of and switching between test cases becomes a matter of a single signal/variable assignment.
  • Read test cases from a file. Switching between test cases becomes a matter of reading from an different file. Test cases can be run in sequence by reading several files in sequence. It’s now possible to add test cases into a version control system separately. A disadvantage is that additional coding and maintenance for the test case files is required.
  • Write reusable procedures and functions to generate the stimuli for the DUT. This is a kind of primitive BFM.

A Git Branching Model

An interesting read about a Git branching model. Not really a novel approach, however still a nice summary on how to use git in the 21st century. Does not point out how to avoid common pitfalls and misses to give some reasoning on why things should be done the way they are shown. Does include a link to a comparison between Git and SVN.

Sneaky Serial Port

Tried out serial communication b/w PC (Windows 7 using hterm) and notebook (Fedora 23 using bash+stty).

Could get data from notebook to PC but not vice versa. Reading from /dev/ttyUSB0 just would not show any received data.

Tried out all combinations of parity bits, stop bits.

Turns out all data arrived but LF was missing, so nothing was displayed in the shell….

That’s one wasted afternoon.

VLSI tools in 500 LOC or Longing for Attention

My VLSI tools take a chip from conception through testing. Perhaps 500 lines of source code. Cadence, Mentor Graphics do the same, more or less. With how much source/object code?

– Chuck Moore, the inventor of Forth –

Now, I’ve seen chip design tools by the likes of Cadence and Mentor Graphics. Astronomically costly licenses. Geological run times. And nobody quite knows what they do.

– http://yosefk.com/blog/my-history-with-forth-stack-machines.html –

Installing Altera Quartus Prime on Fedora 23

Installation did run without problems.
Executing >>quartus from the ~/altera/15.1/quartus/bin folder has no effect whatsoever, no error is printed on the command line.
Adding the above path to $PATH has no effect.
Running >>quartus 2> quartus.stderr to redirect stderr to a file uncovers the following error:

>>cat quartus.stderr
>quartus: error while loading shared libraries: libpng12.so.0: cannot open shared >object file: No such file or directory”

Aha, so a file is missing, why can’t quartus just tell me this?

>>sudo dnf search libpng12
>…
>libpng12.i686 : Old version of libpng, needed to run old binaries
>libpng12.x86_64 : Old version of libpng, needed to run old binaries
>libpng12-devel.i686 : Development files for libpng 1.2
>libpng12-devel.x86_64 : Development files for libpng12
>…

>>sudo dnf install libpng12
>…
>Complete!

Ok let’s try again…

>>quartus

Finally, it works.

Building up a Sound System

Here’s a suggested approach on how to grow your home sound system from a simple stereo system to a full grown 7.1/2 surround sound theater.

  1. Start with a simple stereo system. 2 speakers, front left and front right.
  2. Add a subwoofer for improved bass.
  3. Add a center speaker.
  4. Add 2 speakers, rear left and rear right. This makes a 5.1 system.
  5. Add 2 speakers, effect left and effect right. This makes a 7.1 system.
  6. Add another subwoofer. This makes a 7.2 system.
  7. That’s it.

Testbench != Simulation

There is a difference between testbench files and simulation files:
Testbench files are independent of the simulator and comparable tools. They include testbench configuration files, test case descriptions or stimuli and golden reference output files.

Simulation files are setup and command files for a simulator or similar vendor tool. Related configuration files include waveform settings and simulation scripts.

A project’s folder structure should also draw this distinction to keep simulator/vendor independent files separate. Log files and results should therefor be put in an output folder alongside the testbench files.

 

Spartan3E Starter Board Gotcha

On the Spartan 3E Starter Board the signals A and B of the rotary shaft encoder are actually inverted!
This is not mentioned in the documentation, the figure found there is strongly misleading . At least the pullup resistors are mentioned, which can bring you on the right track.
Oh and remember to put a reset on your FSMs :o)

 

References: Spartan 3E Starter Board documentation

Typical Warez Instructions

1- Unpack, burn or mount
2- Install the game
3- Copy the crack from PROPHET dir
4- Go To Hell!

Accessing ext4 partitions from Windows 7

It is a pain in the ass.

Several Windows tools exist which add support for the file systems used in the Linux world.

  • ext2fs
  • ext2ifs
  • linux reader
  • extfs
  • ext2read

See here for a comparison of existing tools.

However, I can not say that any of these worked properly for ext4. Not to speak of ZFS or btrfs 😉

 

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